1. Field of the Invention
The present invention relates to peripheral circuitry for a memory array, and more particularly to circuitry for use in reading and writing the cells, and restoring the cell bit lines, of a static random access memory (SRAM) array. The invention may be implemented in BICMOS technology.
2. Description of the Related Art
High-speed SRAM arrays are typically constructed of memory cells arranged in rows and columns to form a matrix. The cells of each column are coupled to a pair of bit lines, and the cells of each row are coupled to a word line. The bit lines and word line are coupled to peripheral circuitry for selecting particular columns and rows of cells for the reading or writing of data from or to the cells. A restore or precharge operation is also typically performed over the bit lines after a write operation in order to prepare the column of cells for a new operation and to provide the highest speed.
Thus, the peripheral circuitry servicing a column of SRAM cells generally must be capable of performing at least six different operations--select the column (i.e., select or address the bit lines) for reading; read the cells of that column (i.e., sense the data); select the bit lines for writing data; write a "0" in the cells; write a "1;" and restore the bit lines.
Because these memory operations are so different, prior art circuitry for performing these operations normally has consisted of separate circuits for selecting, reading, writing and restoring. This, however, has several disadvantages. Not only do such individual circuits each contain numerous devices, but they require several different input signals (such as read enable, write enable, chip enable, restore, etc.), and several internal control lines within the array for proper operation and interconnection. For example, at least four separate input lines are often required (namely, bit address, restore, data and data complement), and the circuitry for sensing data for read-out also often requires its own bit address line attachment.
As memories (particularly semiconductor memories) grow in complexity yet shrink in size, the arrays are becoming increasingly crowded. Thus, the number and placement of internal control lines and input/output (I/O) lines is coming under increasing scrutiny. High density and high speed also remain important design criteria for array circuitry for use on a semiconductor chip. There is a growing need, therefore, to simplify the read, write and restore circuitry by reducing the device count, combining functions, reducing the number of control lines and the like, while maintaining high density and high speed.